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TDA7300
DIGITAL CONTROLLED STEREO AUDIO PROCESSOR
SINGLE SUPPLY OPERATION FOUR STEREO INPUT SOURCE SELECTION MONO INPUT TREBLE, BASS, VOLUME, AND BALANCE CONTROL FOUR INDEPENDENT SPEAKER CONTROL (FRONT/REAR) SINGLE SUPPLY OPERATION ALL FUNCTIONS PROGRAMMABLE VIA SERIAL BUS VERY LOW NOISE AND VERY LOW DISTORTION POP FREE SWITCHING DESCRIPTION The TDA7300 is a volume, tone (bass and treble), balance (left/right) and fader (front/rear) procesBLOCK DIAGRAM
DIP28 SO28 ORDERING NUMBERS: TDA7300 TDA7300D
sor for high quality audio applications in car radio and Hi-Fi systems. Control is accomplished by serial bus microprocessor interface. The AC signal setting is obtained by resistor networks and analog switches combined with operational amplifiers. The results are: low noise, low distortion and high dynamic range.
May 1991
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TDA7300
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Supply Voltage (VS1) Operating Ambient Temperature Range Storage Temperature Parameter Value 18 -40 to +85 -40 to 150 Unit V C C
THERMAL DATA
Symbol R th j-pins Description Thermal Resistance Junction-pins Max SO28 85 DIP28 65 Unit C/W
ELECTRICAL CHARACTERISTICS (Tamb = 25C, VS1 = 12V or VS2 = 8.5V , RL = 10k and Rg = 600 , f = 1KHz unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SUPPLY (1)
VS1 VS2 IS2 Vref SVR SVR Supply Voltage VS1 Supply Voltage VS2 Supply Current Reference Voltage (pin 7) Ripple Rejection at VS1 Ripple Rejection at VS2 f = 300Hz to 10KHz f = 300Hz to 10KHz 10 6 15 3.5 80 50 12 8.5 30 4.3 97 58 16 10 40 5 V V mA V dB dB
INPUT SELECTORS
Ri VIN max INS Vi
(DC)
Input Resistance Max. Input Signal Input Separation Input DC Voltage GV = 0dB d = 0.3% f = 1KHz (2) f = 10KHz (2)
30 1.5 90 70 3.5
45 2.2 100 80 4.3 5
K Vrms dB dB V
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ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
VOLUME CONTROLS
Control Range Gmax Max Gain Max Attenuation Step Resolution Attenuator Set Error Tracking Error GV = -50 to 10dB 8 64 78 10 68 2 3 2 2 12 dB dB dB dB dB dB
SPEAKER ATTENUATORS
Control Range Step Resolution Attenuator Set Error Tracking Error 35 38 2 41 3 2 2 15 2.5 3.5 dB dB dB dB
BASS AND TREBLE CONTROL (3)
Control Range Step Resolution dB dB
AUDIO OUTPUT
VO RL CL RO VO(DC) Max. Output Voltage Output Load Resistance Output Load Capacitance Output Resistance DC Voltage Level 3 70 3.8 d = 0.3% 1.5 2 1 150 4.5 2.2 Vrms K nF V
GENERAL
e NO S/N d Output Noise Signal to Noise Ratio Distortion Frequency Response (-1dB) SC Channnel Separation left/right BW = 22Hz to 22KHz, Gv = 0dB Curve A Gv = 0dB All gain = 0dB VO = 1Vrms BW = 22Hz to 22KHz f = 1KHz; VO = 1V; Gv = 0 Gv = 0 f = 1KHz f = 10KHz High Low 20 20 90 70 100 80 6 4 105 0.01 0.1 15
V
dB % KHz Hz dB dB
BUS INPUTS
VIL VIH VO Input LOW Voltage Input HIGH Voltage Output Voltage SDA Acknowledge Digital Input Current I = 1.6mA -5 2.4 0.4 +5 0.8 V V V A
Notes: (1) The circuit can be supplied either at VS1 or without the use of the internal voltage regulator at VS2 . The circuit also operates at a supply voltage VS1 lower than 10V. In this case the ripple rejection of VS2 is valid, because the voltage regulator saturates to a saturation voltage of about 0.8V. (2) The selected input is grounded thru the 2.2F capacitor. (3) Bass and Treble response see attached diagram. The center frequency and quality of the resonance behaviour can be choosen by the external circuitry. A standard first order bass response can be realized by a standard feedback network.
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TDA7300
Figure 1: Application Circuit
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TDA7300
Figure 2: P.C. Board and Components Layout of the Fig.1 (1:1 scale)
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TDA7300
Figure 3: Total Output Noise vs. Volume Setting Figure 4: Signal to Noise Ratio vs. Volume Setting
Figure 5: Distortion + Noise vs. Frequency
Figure 6: Distortion vs. Output Voltage
Figure 7: Distortion vs. Load Resistance
Figure 8: Channel Separation (L1 - R1) vs. Frequency
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TDA7300
Figure 9: Input Separation (L1 - L2) vs. (VS1 ) Frequency Figure 10: Supply Voltage Rejection (VS1) vs. Frequency
Figure 11: Supply Voltage Rejection (VS2 ) vs. Frequency
Figure 12: Supply Voltage Rejection vs. VS1
Figure 13: Supply Voltage Rejection vs. VS2
Figure 14: Clipping Level (Vrms) vs. Supply Voltage
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TDA7300
APPLICATION INFORMATION Volume Control Concept Traditional electronic volume control circuits use a multiplier technique with all the disadvantages of high noise and distortion. The used concept, as shown in Fig. 15 with digital switched resistor dividers, provides extremely low noise and distortion. The multiplexing of the resistive dividers is realized with a multiple-input operational amplifier. Bass and Treble Control The principle operation of the bass control is shown in Fig. 16. The external filter together with the internal buffer allows a flexible filter design according to the different requirements in car radios. The function of the treble is similar to the bass. A typical curve is shown in Fig.19. Outputs A special class-A output amplifier with a modulated sink current provides low distortion and ground compatibility with low current consumption. Figure 17: Quiescent Current vs. Supply Voltage Figure 16: Bass Control
Figure 15: Volume Control
Figure 18: Quiescent Current vs. Temperature
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TDA7300
APPLICATION INFORMATION (continued) Figure 19: Typical Tone Response
Figure 20: Complete Car-Radio System using Digital Controlled Audio Processor
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TDA7300
APPLICATION INFORMATION (continued) SERIAL BUS INTERFACE S-BUS Interface and I2CBUS Compatibility Data transmission from microprocessor to the TDA7300 and viceversa takes place thru the 3wire S-BUS interface, consisting of the three lines SDA, SCL, SEN. If SDA and SEN inputs are short-circuited together, then the TDA7300 appears as a standard I2CBUS slave. According to I2CBUS specification the S-BUS lines are connected to a positive supply voltage via pull-up resistors. Data Validity As shown in fig. 21, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Figure 21: Data Validity on the I2CBUS LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. S-bus: the start/stop conditions (points 1 and 6) are detected exclusively by a transition of the SEN line (1 0 / 0 1) while the SCL line is at the HIGH level. The SDA line is only allowed to change during the time the SCL line is low (points 2, 3, 4, 5). After the start information (point 1) the SEN line returns to the HIGH level and remains unchanged for all the time the transmission is performed. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 23). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer.
Start and Stop Conditions I2CBUS: as shown in fig.22 a start condition is a HIGH to Figure 22: Timing Diagram of S-BUS and I2CBUS
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TDA7300
APPLICATION INFORMATION (continued) Figure 23: Acknowledge on the I2CBUS
Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the P can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity.
Interface Protocol The interface protocol comprises: A start condition (S) A chip address byte, containing the TDA7300 address (the 8th bit of the byte must be 0). The TDA7300 must always acknowledge at the end of each transmitted byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
TDA7300 ADDRESS MSB S 1 0 first byte 0 0 1 0 0 LSB 0 ACK MSB DATA LSB
AC K
MSB DATA
LSB
AC P K
Data Transferred (N-bytes + Acknowledge) ACK = Acknowledge S = Start P = Stop
MAX CLOCK SPEED 100kbits/s
SOFTWARE SPECIFICATION Chip address (TDA7300 address)
1 MSB 0 0 0 1 0 0 0 IIII I LSB
DATA BYTES
MSB 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 B2 0 1 0 1 0 1 1 B1 B1 B1 B1 B1 X 0 1 B0 B0 B0 B0 B0 X C3 C3 A2 A2 A2 A2 A2 S2 C2 C2 LSB A1 A0 A1 A0 A1 A0 A1 A0 A1 A0 S1 S0 C1 C0 C1 C0 Function Volume Control Speaker ATT LR Speaker ATT RR Speaker ATT LF Speaker ATT RF Audio switch Bass control Treble control
Status after power-on reset
Volume Speaker Audio Switch Bass Treble -68dB -38dB Mono +2.5dB +2.5dB
X = don't care Ax = 2dB steps Bx = 10dB steps Cx = 2.5dB steps
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SOFTWARE SPECIFICATION (continued) DATA BYTES (detailed description) VOLUME
MSB 0 0 B2 B1 B0 A2 0 0 0 0 1 1 1 1 0 0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 A1 0 0 1 1 0 0 1 1 LSB A0 0 1 0 1 0 1 0 1 Volume 2dB Steps 0 -2 -4 -6 -8 Not allowed Not allowed Not allowed Volume 10dB steps +10 0 -10 -20 -30 -40 -50 -60
For example if you want setting the volume at -32dB the 8 bit string is: 0 0 1 0 0 0 0 1
SPEAKER ATTENUATORS
MSB 1 1 1 1 0 0 1 1 0 1 0 1 B1 B1 B1 B1 B0 B0 B0 B0 A2 A2 A2 A2 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 A1 A1 A1 A1 0 0 1 1 0 0 1 1 LSB A0 A0 A0 A0 0 1 0 1 0 1 0 1 Speaker LF Speaker RF Speaker LR Speaker RR 0 -2 -4 -6 -8 Not allowed Not allowed Not allowed 0 -10 -20 -30
For example attenuation of 24dB on speaker RF is given by: 1 0 1 1 0 0 1 0
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TDA7300
SOFTWARE SPECIFICATION (continued) AUDIO SWITCH - Select the input Channel to Activate
MSB 0 1 0 X X X X X X X X X X X X X X X X X X S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 LSB S0 0 1 0 1 0 1 0 1 Audio Switch Stereo 1 Stereo 2 Stereo 3 Stereo 4 Mono Not Allowed Not Allowed Not Allowed
X = don't care For example to set the stereo 2 channel the 8 bit string may be: 0 1 0 0 0 0 0 1
BASS AND TREBLE - Control Range of 15dB (boost and cut) Steps of 2.5dB
0 0 1 1 1 1 0 1 C3 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Bass Treble - 15 - 15 - 12.5 - 10 - 7.5 -5 - 2.5 -0 0 2.5 5 7.5 10 12.5 15 15
C3 = Sign For example Bass at -12.5dB is obtained by the following 8 bit string: 0 1 1 0 0 0 1 0
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TDA7300
DIP28 PACKAGE MECHANICAL DATA
DIM. MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 33.02 14.1 0.175 0.130 0.23 1.27 37.34 16.68 0.598 0.100 1.300 0.555 mm TYP. 0.63 0.45 0.31 0.009 0.050 1.470 0.657 MAX. MIN. inch TYP. 0.025 0.018 0.012 MAX.
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TDA7300
SO28 PACKAGE MECHANICAL DATA
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 1.27 16.51 7.6 1.27 8 (max.) 0.291 0.016 18.1 10.65 0.1 0.35 0.23 0.5 45 (typ.) 0.697 0.394 0.050 0.65 0.299 0.050 0.713 0.419 mm TYP. MAX. 2.65 0.3 0.49 0.32 0.004 0.014 0.009 0.020 MIN. inch TYP. MAX. 0.104 0.012 0.019 0.013
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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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